This invention relates to the field of phase locked loop (PLL) frequency multipliers and, more particularly, to methods and apparatus for reducing the overhead associated with activating a PLL by providing an operative clock signal during the lock-time interval of the PLL.
In many computing systems, digital devices, etc., the various clock signals required by a processor are often synchronized to a single reference clock signal and then distributed to the appropriate logic circuits, subsystems and components of the processor. The term processor refers, generally, to any apparatus that performs logic operations, computational tasks, and/or control functions. A processor may include one or more subsystems, components, and/or other processors. A processor will typically include various logic and/or digital components that operate using a clock signal to latch data, advance and/or sequence logic states, synchronize computations and logic operations, and/or provide other timing functions.
A cellular phone, for example, may include a processor having multiple subsystems or components such as a digital signal processor (DSP) operating at a high clock frequency in order to perform real-time, computationally intensive and often time-critical tasks, and a micro-controller (MCU) operating at a lower clock frequency to, for example, carry out various control functions, coordinate events, execute system software, etc. Moreover, the DSP and the MCU may each operate or have supporting components that operate at multiple clock frequencies. The clock frequency requirement at any given time may depend on the computational demands of the processor.
A frequency multiplier implemented by an analog or digital phase-locked loop (PLL) or delay-locked loop (DLL) is often employed to generate a high frequency clock signal and lock it in-phase with a reference clock. The high frequency clock signal may then be supplied to drive a logic circuit or component, provided to a clock distribution tree of a digital device, and/or otherwise distributed to a processor to meet the clocking requirements of the system. Thus, the clock frequency requirements of the various components of a processor may be supported from, and synchronized to, a single reference clock signal.
The term xe2x80x9cprovidedxe2x80x9d in the context of providing a clock signal describes a signal that is not disabled, bypassed, gated off, or otherwise prevented from being applied to, received by, and used for operation by the intended logic gates, digital components and/or circuitry, etc. In general, the term clocked component will be used herein to describe any of the above mentioned components. For instance, a clock signal may be provided to a bypass select, disable logic, clock distribution tree, etc., but is ultimately provided to a one or more low level components such as logic gates, flip-flops etc., requiring a clock as a logic level, a timing signal, a latch, etc. These low level components or collections of such low level components are referred to generally as clocked components.
FIG. 1 illustrates a block diagram of a conventional frequency multiplier 10 that generates an output clock signal from an input clock signal. Frequency multiplier 10 includes a PLL 12 that generates a high frequency output clock signal 32 and locks the signal in phase with input clock signal 30.
The term clock signal, or simply clock, refers generally to any analog or digital periodic signal and, more particularly, a periodic signal used for or used to generate at least one timing signal or logic level for a logic component, digital circuit, or otherwise (i.e., a clocked component). A clock signal may be any of various waveforms including, but not limited to, sinusoids, square waves, pulse trains, etc. For example, a clock signal may be a signal that is ultimately used to advance the state of a processor, latch data, perform logic operations, etc. Signals such as swing sinusoids and signals from, for example, crystal oscillators from which one or more clock signals are formed and/or derived are additionally to be considered clock signals.
PLL 12 includes a phase comparator 22, a loop filter 24, a voltage controlled oscillator 26 and a divider 28. Phase comparator 22 receives an input clock signal 30 and a feedback clock signal 34 and compares the phase of the two signals. Input clock signal 30 may be, for example, a system clock that provides a processor with a reference clock with which to synchronize the higher frequency clock signals distributed to the processor. Feedback signal 34 is related to the output clock signal 32, having substantially the same phase as the output clock signal 32 and substantially the same frequency as the input clock signal 30. Phase comparator 22 provides a phase error signal 40 proportional to the phase difference between the input clock signal 30 and the feedback clock signal 34.
Loop filter 24 provides noise removal and smoothing to the phase error signal 40. For example, loop filter 24 may include a low pass filter. In addition, loop filter 24 transforms the phase error signal 40 into a signal indicating a change in voltage required to reduce the magnitude of the phase error signal 40. Voltage correction signal 42, produced by the loop filter 24, is provided to the VCO to correct for the phase difference between input clock signal 30 and feedback signal 34.
A voltage controlled oscillator (VCO) typically provides a voltage to an oscillator which produces a signal having a frequency proportional to the provided voltage. As such, VCO 26 receives voltage correction signal 42 from loop filter 24 and adjusts a voltage supplied to the oscillator accordingly. The frequency of the output clock signal 32 is thereby adjusted to correct for the phase error detected by the phase comparator 22 (i.e., the output clock signal 32 is urged in-phase with the input clock signal 30).
The output clock signal 32 is fed back to the phase comparator through divider 28. Divider 28 may be, for example, a divide-by-n counter that divides the frequency of the output clock signal to provide feedback clock signal 34 for comparison with the input clock signal 30. As such, the divider ratio n is typically chosen to match the multiplier ratio achieved by the VCO, thus providing the feedback clock signal having substantially the same frequency as the input clock signal and having substantially the same phase as the output clock signal.
Typically, there are various delays associated generating an output clock signal that is phase-locked to an input clock signal. In particular, there is an interval of time required for the phase-locked loop to converge (i.e., to lock the output clock signal in-phase with the input clock signal). The delay incurred while acquiring phase lock is often referred to as lock time.
FIG. 2 depicts a timing diagram illustrating delays often associated with generating an output clock signal that is phase-locked to an input clock signal by means of a frequency multiplier such as that illustrated in FIG. 1. Plot 5 illustrates the frequency of an output clock signal (e.g., output clock signal 32) as a function of time. In FIG. 2, it will be assumed that the PLL is not active at time t0. For example, no input clock signal is provided to the PLL, the VCO is not enabled, and no output clock signal is generated. In other words, time t0 signifies the moment when it is first desired to supply an input clock to the frequency multiplier and power up the VCO, that is, when it is desired to activate the PLL.
A finite amount of time may be required before a stable input clock can be provided to the phase comparator of the PLL. This time is part of an interval, referred to as wake-up time, and indicated as interval 60. Different PLL or DLL implementations may have other delays associated with the wake-up time. For instance, in the PLL of FIG. 1, there may be a delay associated with enabling the VCO to begin providing a voltage to the oscillator. In general, wake-up time refers to the interval of time associated with enabling the various signals and/or components of the PLL. In particular, wake-up time refers to the interval of time between the moment it is desired to generate an output clock signal and the time the signal generator first outputs a signal.
In addition, there may be delays associated with the time required for the PLL to acquire phase lock between an input and an output clock signal. These delays are indicated as time intervals 64 and 66, referred to as PLL lock time and PLL lock timer, respectively. Time interval 64 indicates the actual time necessary to acquire a phase lock between the input clock signal and the output clock signal. However, it is often difficult to precisely detect when the PLL has been effectively locked. To complicate this matter, the actual lock time may vary as function of the desired frequency increase of the multiplier, the amount of noise in the input clock signal, etc. As such, there may be a degree of uncertainty in predicting the lock time of a PLL.
To combat the uncertainty involved in detecting and/or predicting the actual lock time, a lock timer may be employed to record an interval of time equal to or beyond the worst case lock time of the PLL. The lock timer begins to count down when the PLL is first activated. Typically, the PLL will not be considered locked and stable until the lock timer expires. Accordingly, the latency of a frequency multiplier is often constrained by the delay recorded in the lock timer (e.g., interval 66). The term latency refers, generally, to an interval of time that elapses before an operative clock signal is output from a frequency multiplier.
An operative clock signal refers to a clock signal that may be provided to a clocked component in order to perform its intended function. In general, an operative clock signal provides a useable timing reference and/or logic signal such that useful computation and/or processing may be performed without loss of data or other deleterious effects. For example, an operative clock signal may be a clock signal that is sufficient to advance a processor, latch data, synchronize logic events, and/or perform other logic operations requiring a clock signal without operating outside the tolerances of the clocked components and without causing the clocked components to operate erroneously.
Various methods have been proposed to decrease the latency of a frequency multiplier. However, these methods often focus on reducing the lock time of the phase locked loop, and as a result, reducing the delay required by the lock timer to accommodate the worst case lock time.
Applicants herein have observed that the latency obtained by methods of reducing the frequency multiplier lock-time may still suffer from significant loss of processing time and power consumption while the system waits for the frequency multiplier to acquire phase lock. In addition, some processing situations may require a frequency multiplier having a latency smaller than that obtained by methods of reducing the lock time.
Accordingly, one embodiment according to the present invention includes a method of reducing the overhead of activating a frequency multiplier providing a first output clock signal to be synchronized to an input clock signal. The method comprises acts of providing an input clock signal having a first frequency to the frequency multiplier with which to synchronize the first output clock signal, generating the first output clock signal having a second frequency that substantially converges to a target frequency, the target frequency greater than the first frequency, the generation of the first output clock signal determining the beginning of a lock time interval, generating a second output clock signal from the first output clock signal, the second output clock signal having a third frequency that is less than the second frequency and not exceeding the target frequency, determining when the first output clock signal is synchronized with the input clock signal, the determination of synchronization ending the lock time interval, and providing the second output clock signal to at least one clocked component during the lock time interval and providing the first output clock signal to the at least one clocked component after the lock time interval.
Another embodiment according to the present invention includes a method a method of providing an operative clock signal during a lock time interval of a frequency multiplier adapted to provide an output clock signal synchronized to an input clock signal. The method comprises acts of reducing a phase difference between the input clock signal and the output clock signal to essentially zero by coupling the input clock signal and the output clock signal in a feedback control loop. During the act of reducing the phase difference between the input clock signal and the output clock signal, the method further comprises acts of dividing a frequency of the output clock frequency by N to provide a reduced frequency clock signal, and providing the reduced frequency clock signal to at least one clocked component only after detecting that a frequency of the reduced frequency clock signal has exceeded a predetermined threshold frequency.
Another embodiment according to the present invention includes a comparator to receive an input clock signal having a first frequency and a feedback signal, the comparator adapted to provide an error signal indicative of a difference in a first property of the input clock signal and the feedback signal, a signal generator coupled to the comparator to provide an output clock signal having a second frequency, the generator adjusting a second property of the output clock signal based on the error signal to reduce the difference in the first property of the input clock signal and the feedback signal, a feedback loop providing the feedback signal from the output clock signal to the comparator, the feedback loop having associated with it a first interval of time required in order to reduce the difference in the first property between the input clock signal and the output clock signal to essentially zero, and means for providing an operative signal from the output clock signal during the first interval of time.
Another embodiment according to the present invention includes a frequency multiplier adapted to provide an operative clock signal before an output clock signal has been synchronized to an input clock signal. The frequency multiplier comprises a comparator to receive an input clock signal having a first frequency and a feedback signal, the comparator adapted to provide an error signal indicative of a difference in a first property between the input clock signal and the feedback signal, a signal generator coupled to the comparator to provide an output clock signal having a second frequency, the generator adjusting a second property of the output clock signal based on the error signal to reduce the difference in the first property between the input clock signal and the feedback signal, a first divider to reduce the second frequency to generate the feedback clock signal provided to the phase comparator, a second divider to divide the second frequency by N to provide a second output clock signal having a third frequency, and a detector adapted to monitor at least one of the first output clock signal and the second output clock signal, the detector configured to provide the second output clock signal to at least one clocked component only after the detector has determined that the third frequency has exceeded a predetermined threshold frequency, the predetermined threshold frequency greater than the first frequency.